NextSilicon Unveils Maverick-2: A New Era in High-Performance Computing Accelerators
NextSilicon, a technology startup established in 2017, has introduced its latest innovation in high-performance computing (HPC) and artificial intelligence (AI) acceleration: the Maverick-2 Intelligent Compute Accelerator (ICA). Built on TSMC’s advanced 5 nm process, Maverick-2 is designed to deliver exceptional computational efficiency and performance, targeting demanding workloads in scientific computing, AI, and data analytics.
Maverick-2 Architecture and Performance
The Maverick-2 accelerator is available in two configurations: a single-die PCIe card equipped with 96 GB of HBM3e memory (operating at 300 W), and a dual-die OAM version featuring 192 GB of HBM3e (at 600 W). According to NextSilicon’s internal benchmarks, Maverick-2 achieves up to four times higher FP64 performance-per-watt compared to NVIDIA’s HGX B200 GPU, and over 20 times greater efficiency than Intel’s Xeon Sapphire Rapids CPUs.
In GUPS (Giga Updates Per Second) benchmarks, Maverick-2 reached 32.6 GUPS at 460 W, which the company reports is 22 times faster than leading CPUs and six times faster than top-tier GPUs. For HPCG (High Performance Conjugate Gradients) workloads, the accelerator delivered 600 GFLOPS at 750 W, while consuming approximately half the power of competing solutions.
These performance gains are attributed to Maverick-2’s data-flow based architecture. Unlike traditional accelerators that rely heavily on hardware for overhead management, Maverick-2 shifts much of this responsibility to adaptive software. This approach allows a greater proportion of the silicon area to be dedicated to computation, reducing the footprint of control logic and maximizing throughput.
Introducing Arbel: NextSilicon’s RISC-V Enterprise Chip
Alongside Maverick-2, NextSilicon has announced Arbel, an enterprise-grade processor based on the open RISC-V instruction set architecture and also manufactured on TSMC’s 5 nm node. The company claims that Arbel outperforms current RISC-V designs as well as Intel’s Lion Cove and AMD’s Zen 5 cores.
Arbel features a 10-wide instruction pipeline and a 480-entry reorder buffer, enabling high core utilization and efficient parallel execution. Operating at 2.5 GHz, the chip can process up to 16 scalar instructions simultaneously and includes four 128-bit vector units optimized for data-parallel workloads. With a 64 KB L1 cache and a large shared L3 cache, Arbel is engineered to deliver high memory throughput and low latency, minimizing bottlenecks in compute-intensive applications.
While NextSilicon has not yet provided a release date or comprehensive benchmark results for Arbel, the company positions it as a step toward a fully open, software-adaptive silicon platform tailored for the next generation of HPC and AI systems.
Advancing the Future of HPC and AI
NextSilicon’s latest announcements highlight a shift in high-performance computing hardware design, emphasizing software-adaptive architectures and open standards. With Maverick-2 and Arbel, the company aims to set new benchmarks in computational efficiency and flexibility, addressing the evolving needs of scientific research, enterprise AI, and data-intensive workloads.
